A memory block of a memory device, such as a NAND memory, may comprise a group of strings of charge storage devices that share the same set of access lines. The memory block may be grouped into a plurality of pages, and each page may comprise all or a subset of the charge storage devices corresponding to a respective tier of each of the group of strings, for example, depending on whether the charge storage devices are single-level cells or multi-level cells.
Under existing semiconductor memory techniques, a memory operation may be performed on an entire memory block (e.g., if the memory operation is an erase), or on a page within the memory block (e.g., if the memory operation is a program, read or verify). Accordingly, as the page size becomes larger, the power used during a data line swing or page buffer flip may increase, so that a relatively large amount of power may be consumed when relatively small amounts of data, such as 4 KB, are read, programmed, erased or verified. This tendency may be enhanced when an ABL (all-bit line) architecture is used, in comparison with a SBL (shielded bit line) architecture. Thus, as the size of the memory block or page increases, so does the current consumption and/or parasitic current leakage when memory operations are performed.
This problem may be aggravated in three-dimensional (3D) memory devices. For example, in a 3D memory device, wiring for a plurality of control gates (CGs) or source select gates (SGSs) of the strings may be physically merged into what is hereinafter sometimes referred to as a “plate” that may comprise a plurality of horizontal CGs or SGSs, such as 16 CGs or 16 SGSs merged together. While reducing the number of high-voltage driver transistors needed to bias the CGs or SGSs (or other elements in the 3D memory device) to a certain signal (e.g., voltage), this also increases the number of charge storage devices in the memory block or page on which the memory operation may be performed concurrently. Thus, the memory block or page upon which the memory operation is performed may cause extensive current consumption and/or parasitic current leakage. This, in turn, may incur the need to supply the memory device with additional and/or alternative power sources to support the extensive current consumption and/or parasitic leakage.